Optimizing PPA with RISC-V custom extensions in TWS earbuds

In a recent TWS market study, SAR finds that the use of RISC-V cores is increasing. The RISC-V is license free core although one has sole responsibility to make the core run without any technical issues.

Fabless TWS SoC companies such as mid-to-low tier IC companies may find RISC-V cores appealing due to the cost saving reason as they do not have to a pay license fee, unlike ARM cores.

Andes Technology is one of the early companies supporting RISC-V cores and they are one of the founding members of RISC-V International Association.

It is expected that more and more design service companies may choose to provide RISC-V core implementation such as Andes Technology. Ceva, Cadence and Synopsys may choose to participate in the support of RISC-V even though they may already have their own CPU core implementation.

SAR’s latest TWS market study covers CPU cores being used in the TWS SoCs that are in the market.

Dr. Seongcheol Jang Director, Voice Technologies

Dr. Jang is Director of SAR’s UI Practice Area, providing market insights on the latest devices, software, and components.

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